1. Field of the Invention
The present invention relates to a communication apparatus which performs frequency conversion processing and to a signal processing apparatus advantageously used for the frequency conversion processing of the communication apparatus.
2. Description of the Related Art
Conventional receivers for high frequency radio multiplex communication or high frequency wired multiplex communication are provided with circuits for performing frequency conversion. Examples of such receivers are a portable telephone terminal, an automobile telephone terminal, a transceiver, a television broadcasting receiver, a radio broadcasting receiver, a cable television (CATV) receiver and the like.
FIG. 16 is a block diagram illustrating an electrical configuration of an FM (Frequency Modulation) radio receiver 1 according to a prior art. The FM radio receiver 1 uses a plurality of channels within a predetermined frequency band, and is utilized in a radio communication network which transmits carrier waves frequency-modulated by base band signals to a plurality of FM radio receivers, respectively, in parallel. The FM radio receiver 1 is, for example, used as a receiver unit of a portable telephone terminal in an analogue portable telephone network.
The FM radio receiver 1 is of a double-super-heterodyne system including an antenna 3, a high-frequency filter 4, a low noise amplifier 5, a first and a second frequency converting units 6, 7, an oscillation source 8, a first and a second intermediate frequency filters 9, 10, an amplifier-limiter 11, an FM demodulation unit 12, a base band voice processing unit 13, a speaker 14 and a control unit 15. The first and the second frequency converting units 6, 7 include first and second mixers 16, 18 and first and second local frequency oscillators 17, 19, respectively.
The antenna 3 receives an electromagnetic wave and outputs a receive signal corresponding to the received electromagnetic wave. After signal components outside the predetermined frequency band are removed by the high frequency filter 4, the receive signal is amplified by the low noise amplifier (LNA) 5, and then supplied to the first mixer 16. The first local frequency oscillator 17, using a reference oscillation signal having a predetermined reference frequency oscillated by the oscillation source 8, generates a first local oscillation signal having a frequency defined based on a designated frequency designated by an operator of the FM radio receiver 1 or a predetermined designated frequency, and the frequency of the receive signal to supply it to the first mixer 16.
The first mixer 16 mixes the first local oscillation signal and the receive signal to generate a first intermediate frequency signal having a predetermined first intermediate frequency. The first intermediate frequency filter 9 performs filtering of passing only components within a frequency band of a predetermined band width including the designated frequency from the first intermediate frequency signal for channel selection. After being filtered, the first intermediate frequency signal is supplied to the second mixer 18.
The second local frequency oscillator 19, using the reference oscillation signal, generates and outputs a second local oscillation signal based on the frequency of the intermediate frequency signal after filtering and a second intermediate frequency. The second mixer 18 mixes the second local oscillation signal and the first intermediate frequency signal after filtering, and generates a second intermediate frequency signal having a predetermined second intermediate frequency. The second intermediate frequency filter 10 performs filtering for passing only components of the channel including the designated frequency from the second intermediate frequency signal for channel selection. The second intermediate frequency signal after filtering is supplied to amplifier-limiter 11.
The amplifier-limiter 11 amplifies the second intermediate frequency signal after filtering, and limits the amplitude of the second intermediate signal after amplification so as to remove amplitude modulation (AM: amplitude modulation) components. The FM demodulation unit 12, to reconstruct the base band signal, performs frequency discrimination on the second intermediate frequency signal after amplitude limitation. The base band voice processing unit 13 performs a processing defined in the radio communication network on the resultant signal of the frequency discrimination, and supply the signal to the speaker 14 or the control unit 15. The speaker 14 electroacoustically converts the signal after the processing to output the resultant sound. In the case where the signal after the processing represents protocol control data or user data, the control unit 15, based on the data, performs processing relating to the control of the entire FM radio receiver 1. The above describes the FM radio receiver 1.
In the FM radio receiver 1, the high frequency filter 4 and the first and the second intermediate frequency filters 9, 10 are generally formed of a dielectric material or ceramic material, and the low noise amplifier 5, the amplifier-limiter 11, the FM demodulation unit 12, the base band voice processing unit 13 and the first and the second mixers 16, 18 are implemented by semiconductor elements. Therefore, it is difficult to integrate the high frequency filter 4 and the first and the second intermediate frequency filters 9, 10 with the low noise amplifier 5, the amplifier-limiter 11, the FM demodulation unit 12, the base band voice processing unit 13 and the first and the second mixers 16, 18 into one integrated circuit.
Recently, radio communications utilizing a higher frequency band such as a G (giga) Hz band than that of the conventional radio communications have been proposed. To apply a communication apparatus with the same configuration as the FM radio receiver 1 for the radio communication using GHz band, each component of the communication apparatus is required to operate at a higher operating frequency than that of the conventional FM radio receivers. Generally, in the case where each of the filters 4, 9, 10 is implemented by a semiconductor circuit, that is, each of the filters 4, 9, 10 is implemented by a so-called digital filter, when the filters 4, 9, 10 are operated at the operating frequency proper to the radio communication using the GHz band, there is often the case that characteristics required for the radio communication is not obtained. This is because, the upper limit operating frequency of the semiconductor circuit is determined due to the configuration and the characteristics of the circuit itself, and if the circuit is operated at a frequency higher than the upper limit operating frequency, the operation will become unstable.
Japanese Unexamined Patent Publication JP-A 9-135149 (1997) discloses that, in a digital filter which performs digital filtering for processing digital coded signals, a technology to reduce the operating frequency of components within the digital filter. The digital filter includes one input portion, one switch, a plurality of FIFO type memories and a plurality of multipliers. A plurality of sets of objective data to be processed are acquired by sampling a signal to be inputted at an input sampling frequency Fe.
The objective data to be processed arrives at the input portion sequentially with the input sampling frequency Fe. The switch is interposed between the input portion and each of the memories, and in response to the arrival of the data, distributes the plurality of sets of data into the plurality of memories to be stored therein. Each of the multipliers operates according to a clock signal of a clock frequency which is L/M times the input sampling frequency Fe, and determines each of the product of the data memorized in each of the memories and one of plurality of predetermined coefficients. The above mentioned any one of the coefficients are changed whenever one period of the clock signal passes. Both L, M are integers and L/M is a value less than one.
In the digital filter disclosed in JP-A 9-135149, the switch operates at the input sampling frequency. Therefore, in the case where the components constituting the digital filter are integrated to form one integrated circuit, if the input sampling frequency is raised to the GHz band, for example, there is a possibility that the operation of the switch becomes unstable. Therefore, it is difficult to integrate the digital filter and use it for the GHz band radio communication.
Japanese Unexamined Patent Publication JP-A 6-46010 (1994) discloses, in an apparatus which performs sampling of analogue signal and arithmetic processing using the result of sampling, a technique to perform these sampling and arithmetic processing at a speed higher than the operating speed specific to that apparatus. The digital signal processing apparatus in this patent publication is configured by arranging a plurality of processing units in parallel, each processing unit being constituted of an analogue/digital converter, an arithmetic circuit and a digital/analogue converter connected in series, and causes the plurality of processing units to operate based on a plurality of clock signals of different phases, respectively. The digital signal processing apparatus of JP-A 6-46010 includes a plurality of analogue/digital converters, a plurality of arithmetic circuits, a plurality of digital/analogue converters and a clock signal oscillator. Consequently, the number of components constituting the apparatus become large, so that it is difficult to miniaturize the apparatus and also the costs tend to rise.
Japanese Unexamined Patent Publication JP-A 10-163912 (1998) discloses, in a radio receiver, a sampling apparatus for converting the frequency of an inputted modulation signal to a frequency lower than that frequency. The sampling apparatus, first, samples a modulation signal at a sampling frequency which is higher than the signal band of the modulation signal, and performs decimation processing on the resultant signal of the sampling, and again, samples the signal after decimation processing to output the resultant signal. The sampling frequency of the first sampling is concretely twice as high frequency as the signal band of the modulation signal. The sampling frequency of the second sampling is lower than the sampling frequency of the first sampling.
In this way, in the sampling apparatus described above, since the modulation signal is sampled at the frequency higher than twice the signal band of the modulation signal, the higher the signal band of the modulation signal is, the higher the operating frequency of the circuit conducting the first sampling needs to be raised. Therefore, the higher the signal band of modulation signal is, the more difficult it is to lower the operating frequency of the sampling circuit. Still more, in the sampling apparatus described above, at the sampling of signal, is used a plurality clock signals which are different both in period and phase from each other. The configuration of the circuit which generates such clock signals tends to be complex.
An object of the invention is to provide a signal processing apparatus capable of operating at an operating frequency lower than a sampling frequency required for signal processing and of being readily miniaturized, and a communication apparatus using the signal processing apparatus.
In a first aspect, the invention provides a signal processing apparatus comprising:
clock signal generating means for generating a plurality of clock signals of which frequencies are mutually equal and of which phases are different from each other;
a plurality of sampling means to which an input signal including signal components as processing objects within a predetermined input frequency band is supplied in parallel, the sampling means sampling the input signal according to any one of the plurality of clock signals and outputting the sampled input signals sequentially as sample signals;
sum-of-products operating means for periodically finding, with a timing based on an operating frequency which is equal to the frequency of the plurality of clock signals, a total sum of products of each of the sample signals outputted from all of the sampling means respectively and each of a plurality of predetermined multiplication coefficients; and
output filter means for only passing components within an output frequency band which is different from the input frequency band, in a sum-of-products signal which is constituted of the total sums of products aligned in order of being found.
According to the first aspect of the invention, the signal processing apparatus causes the plurality of sampling means sample one input signal. Since the clock signals supplied to the respective sampling means have phases different from each other, every sampling means samples the input signal once, while one period of the clock signal elapses. As a result, a multiphase sample signal constructed by aligning the sample signals outputted from all of the sampling means in order of being sampled becomes equal to the signal that is obtained by sampling the input signal at an effective sampling frequency higher than the frequency of the clock signals.
And the sum-of-products operating means performs sum-of-products operation for the multiphase sample signal based on the operating frequency equal to the frequency of the clock signals. Accordingly, any one of the plurality of clock signals or a clock signal of which frequency is equal to that of the plurality of clock signals and of which phase is different from that of the plurality of clock signals is supplied to the sum-of-products operating means, and the sum-of-products operating means operates based on the supplied clock signal. The sum-of-products operation is an operation for implementing a so-called digital filter or the like. As a result of this, the sum-of-products signal is the one which is derived by performing so-called decimation processing on the processing result of the sum-of-products operation, and thus includes reflected components of the signal components as processing objects. Since the output frequency band is different from the input frequency band, the output filter means only passes the reflected components within the sum-of-products signal as an output signal. Consequently, the output signal becomes equivalent of the signal obtained by frequency conversion of the input signal.
As described above, the signal processing apparatus can perform frequency conversion on the input signal which should be processed at the effective sampling frequency, by using the clock signals of which frequency is lower than the effective sampling frequency. Each of the sampling means and the sum-of-products operating means can both be implemented by a semiconductor circuit, and the output filter means can also be implemented by a semiconductor circuit as a so-called digital filter. Therefore, the signal processing apparatus can be configured only using semiconductor circuits of which upper limit operating frequency is lower than the effective sampling frequency. As a result, the signal processing apparatus can be configured only by semiconductor circuits, and it is possible to easily and stably covert the frequency of the signals which should be processed with a frequency higher than the upper limit operating frequency defined due to the configuration and the characteristics of the semiconductor circuits. For this reason, the signal processing apparatus is integrated easier than the conventional signal processing apparatus for frequency conversion using a local oscillator, a mixer and a filter formed of a ceramic material or dielectric material. Accordingly, the signal processing apparatus is easy to be miniaturized and to be lowered in its manufacturing costs.
In a second aspect of the invention, it is preferable that the signal processing apparatus further comprises multiplication coefficient changing means for changing each of the plurality of multiplication coefficients.
According to the second aspect of the invention, the signal processing apparatus further comprises the multiplication coefficient changing means in addition to the configuration of the signal processing apparatus of the first aspect of the invention. In the case where the sum-of-products operating means implements a digital filter, the filter characteristics of the digital filter changes as the multiplication coefficient change is changed. Therefore, by providing the multiplication coefficient changing means, it is possible to change the filter characteristics of the digital filter easily.
In a third aspect of the invention, it is preferable that the signal processing apparatus further comprises a plurality of re-sampling means interposed between the plurality of sampling means and the sum-of-products operating means, respectively, for sampling the sample signal outputted from each of the sampling means based on a clock signal delayed in phase from the clock signal supplied to each of the sampling means to output it to the sum-of-products operating means, wherein the clock signals supplied to each of the sampling means are mutually equal.
According to the third aspect of the invention, the signal processing apparatus further comprises the plurality of re-sampling means in addition to the configuration of the signal processing apparatus of the first aspect of the invention. Since the clock signals supplied to each of the re-sampling means are mutually equal, each of the re-sampling means supplies the sum-of-products operating means with the sample signal after re-sampling at the same time. Therefore, since the sample signals supplied to the sum-of-products operating means are in phase with each other, it is easy for the sum-of-products operating means to synchronize the operation timing between a plurality of the sampling means.
In a fourth aspect of the invention, it is preferable that the frequency of the clock signals is equal to or less than twice the upper limit frequency of the input frequency band; and
the output frequency band is lower than the input frequency band.
According to the fourth aspect of the invention, the signal processing apparatus of the first aspect of the invention is configured so that the frequency of the clock signals is equal to or less than twice the upper limit frequency of the input frequency band; and the output frequency band is lower than the input frequency band. As a result, in the sum-of-products signal, the reflected components appear in a bandwidth lower than the input frequency band, and the output filter means only pass the reflected components within the lower band. Accordingly, the signal processing apparatus according to the fourth aspect of the invention can down-convert the input signals.
In a fifth aspect of the invention, it is preferable that the signal processing apparatus further comprises buffer amplification means provided in the previous stage of all of the sampling means.
According to the fifth aspect of the invention, the signal processing apparatus further comprises the buffer amplification means in addition to the configuration of the signal processing apparatus of the first aspect of the invention. Accordingly, the signal processing apparatus according to the fifth aspect of the invention can reduce interference noise among the plurality of sampling means. Further accordingly, the signal processing apparatus can reduce the effect of an input capacity of the plurality of sampling means on the input signal. As a result of above, the signal processing apparatus can operate with stability even when the effective sampling frequency is raised.
In a sixth aspect of the invention, it is preferable that the signal processing apparatus further comprises halt indication means for indicating a halt of sampling of the input signal, wherein the clock signal generating means halts the generation of clock signals while the halt indication means indicates the halt of sampling.
According to the sixth aspect of the invention, the signal processing apparatus further comprises a configuration regarding the control of the clock signal generating means in addition to the configuration of the signal processing apparatus of the first aspect of the invention. When the clock signals are not generated, all of the sampling means and the sum-of-products operating means halt the operations. As a result, the signal processing apparatus according to the sixth aspect of the invention can lower the power consumption consumed during the period where processing for input signal is not required in comparison with the case where clock signals are generated during the period.
In a seventh aspect of the invention, it is preferable that the plurality of clock signals are 4-phase clock signals.
According to the seventh aspect of the invention, in the signal processing apparatus of the first aspect of the invention, the clock signal generating means generates 4-phase clock signals. The 4-phase clock signals can easily be generated by using a so-called sine/cosine oscillation circuit. Therefore, the circuit scale of the clock signal generating means is reduced further than the case where clock signals other than 4-phase clock signals are generated. Consequently, the signal processing apparatus according to the seventh aspect of the invention can be reduced in the circuit scale, so that it is easy to miniaturize and reduce the manufacturing costs, and also it is possible to reduce the power consumption. Accordingly, the signal processing apparatus has a configuration suitable for integrating the entire signal processing apparatus to form a single integrated circuit.
In an eighth aspect of the invention, it is preferable that the signal processing apparatus further comprises a plurality of memory elements which are respectively connected in series to the next stage of each of the sampling means,
wherein each of the sampling means supplies the sample signal to the sum-of-products operating means and at the same time stores the sample signal in the memory element in the next stage of the sampling means, and
each of the memory elements transfers the stored sample signal to the memory element of the next stage to store therein, with a timing defined based on the clock signal supplied to each of the sampling means in the previous stage of each of the memory elements, and gives the sample signal to the sum-of-products operating means.
According to the eighth aspect of the invention, the signal processing apparatus further comprises a plurality of the memory elements in addition to the configuration of the signal processing apparatus according to the first aspect of the invention. Accordingly, the past sample signal obtained by the past sampling by each of the sampling means and the latest sample signal obtained by the present sampling of each of the sample signals are at the same time supplied to the sum-of-products operating means. Consequently, the sum-of-products operating means can perform sum-of-products operation based on the sample signals larger in number than the sampling means.
In a ninth aspect, the invention provides a communication apparatus comprising:
receiving means for receiving the input signal;
the signal processing apparatus according to any one of the first to eighth aspect of the invention; and
demodulation means for demodulating an output signal outputted from the output filter means in the signal processing apparatus.
According to the ninth aspect of the invention, the communication apparatus performs frequency conversion on the received input signal by the signal processing apparatus, and demodulates the input signal after frequency conversion to obtain a desired base band signal. Consequently, in the communication apparatus, it is possible to perform frequency conversion of the input signal by means of circuit components which operate on the basis of based on the clock signal of a frequency lower than the effective sampling frequency. Therefore, since the signal processing apparatus is easy to be miniaturized and integrated, the communication apparatus is also easy to be miniaturized, to be integrated and to be reduced in its manufacturing costs.
In a tenth aspect of the invention, it is preferable that the communication apparatus further comprises intermediate filter means provided in the previous stage of the plurality of sampling means, and a plurality of intermediate sampling means interposed between the receiving means and the intermediate filter means,
wherein each of the intermediate sampling means samples the input signal according to any one of all the clock signals, respectively, and sequentially outputs part of the input signal as an intermediate sample signal;
each of the intermediate filter means only passing signal components within a predetermined passing frequency band in an intermediate signal constructed by aligning the intermediate sample signals outputted from all of the intermediate sample means respectively in order of being sampled; and
each of the sampling means samples the signal components within the passing frequency band in the intermediate signal.
According to the tenth aspect of the invention, the communication apparatus further comprises a configuration for frequency conversion in addition to the configuration of the communication apparatus according to the ninth aspect of the invention. As a result, the communication apparatus according to the tenth aspect of the invention has two means for performing operational processing for implementing a digital filter, which permits the processing for removing signal components of a given frequency band from the input signal at the same time as the frequency conversion processing. Accordingly, the two digital filters within the communication apparatus share the necessary role within the communication apparatus, resulting that the two digital filters are readily designed.
In an eleventh aspect of the invention, it is preferable that the communication apparatus further comprises:
detector means for detecting amplitude modulation components in the input signal; and
filter controlling means which discriminates whether interference components interfering the signal components as processing objects are included in the input signal based on the detected amplitude modulation components, and only when the interference components are included, changes frequency characteristics of at least any one of the sum-of-products operating means, the intermediate filter means and the output filter means, to frequency characteristics for removing the interference components.
According to the eleventh aspect of the invention, the communication apparatus further comprises, in addition to the configuration of the communication apparatus according to the tenth aspect of the invention, a configuration for changing the frequency characteristics of at least one of the means among the sum-of-products operating means, the intermediate filter means, and output filter means. Accordingly, the communication apparatus according to the eleventh aspect of the invention, by way of at least one of the means, can remove the interference components from the input signal, in the case where the receiving means receives the signal components as processing objects and the interference components at the same time. Therefore, the receive performance of the communication apparatus increases. And all of the three means are a so-called digital filter. By adjusting the multiplication coefficient of the arithmetic processing of a digital filter, it is easy to change the frequency characteristics such as a pass band and a center frequency of the digital filter. In the communication apparatus, it is possible to readily set the frequency characteristics of at least one of the three means in response to the frequency band where the interference components exist. Therefore, the communication apparatus increases in its receive performance.
In a twelfth aspect of the invention, it is preferable that a frequency of the output signal is equal to an effective sampling frequency which is the product of the frequency of the clock signals and the number of the sampling means, or equal to the frequency which is one integers of the effective sampling frequency.
According to the twelfth aspect of the invention, in the communication apparatus according to the ninth aspect of the invention, the relationship between the clock frequency of the output signal and the effective sampling frequency is as described above. Consequently, a corresponding relationship between the sample signals outputted from each of the sampling means and a variable to be subscribed for each of the sample signals in the arithmetic expression indicating the arithmetic processing of the sum-of-products operating means is fixed. Accordingly, the communication apparatus according to the twelfth aspect of the invention can reduce the number of the sampling means appropriately according to the configuration of the arithmetic expression, in comparison with other types of communication apparatus as an object for comparison which lacks the above described relationship between the clock frequency of the output signal and the effective sampling frequency, and, can eliminate the circuits to generate clock signals which are supposed to be supplied to the omitted sampling means.
In a thirteenth aspect of the invention, it is preferable that an order of the sum-of-products operating means which is smaller by one than the number of sample signals used for one-time arithmetic processing thereof is smaller than a decimation number which is a ratio of the frequency of the sum-of-products signal to the frequency of a multiphase sample signal constructed by aligning the sample signals in time order of being sampled.
According to the thirteenth aspect of the invention, in the communication apparatus of the twelfth aspect of the invention, the communication apparatus has a configuration where the sum-of-products operating means performs one sum-of-products arithmetic processing using the sample signals of the number smaller than the decimation number. The decimation number is equal to the number of sample signals obtainable during one period of the clock signal, when the input signal is actually sampled at the effective sampling frequency. Consequently, in the communication apparatus according to the thirteenth aspect of the invention, the number of sampling means can be smaller than the decimation number and the clock signal generating means can be simplified. Accordingly, the communication apparatus can reduce the current consumption during the operation. And accordingly, in the case where the signal processing apparatus is integrated to form one integrated circuit, it is possible to miniaturize the integrated circuit and to reduce the manufacturing costs readily.
In a fourteenth aspect of the invention, it is preferable that the sum-of-products operating means performs arithmetic processing for implementing a finite impulse response FIR filter and that at least one of the plural multiplication coefficients in the arithmetic processing is zero.
According to the fourteenth aspect of the invention, in the communication apparatus according to the twelfth aspect of the invention, the sum-of-products operating means of the communication apparatus is a finite impulse response FIR filter with a coefficient of zero. Consequently, the communication apparatus according to the fourteenth aspect of the invention can omit sampling means for obtaining sample signals which should be multiplied by the coefficient of zero and part of the multiphase clock generating means for generating clock signals which should be supplied to the sampling means. Accordingly, the communication apparatus can reduce the current consumption during the operation. And accordingly, in the case where the signal processing apparatus is integrated to form one integrated circuit, the communication apparatus is easier in miniaturizing the integrated circuit and in eliminating the manufacturing costs than the communication apparatus before the omission.